Stress Management in Sub-90-nm Transistor Architecture

Research output: Contribution to journal › Article › peer-review

Original language	American English
Pages (from-to)	1740-1743
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	51
Issue number	10
DOIs	https://doi.org/10.1109/TED.2004.835993
State	Published - 2004

NLR Publication Number

@article{19c69be2aae74a52ba96e7b37b69670d,

title = "Stress Management in Sub-90-nm Transistor Architecture",

author = "NREL",

year = "2004",

doi = "10.1109/TED.2004.835993",

language = "American English",

volume = "51",

pages = "1740--1743",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}